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? 2008 semiconductor components industries, llc. publication order number: fan3214 /d october-2017, rev.2 fan32 13 / fan32 14 dual - 4 a , high - speed , low - side gate drivers fan32 13 / fan32 14 dual-4 a, high-speed, low-side gate drivers features ? industry-standard pin out ? 4.5 to 18 v operating range ? 5 a peak sink/source at v dd = 12 v ? 4.3 a sink / 2.8 a source at v out = 6 v ? ttl input thresholds ? tw o versions of dual independent drivers: - dual inverting (fan32 13 ) - dual non-inverting (fan3214) ? internal resistors turn driver off if no inputs ? millerdrive? technology ? 12 ns / 9 ns typical rise/fall times w ith 2.2 n f load ? typical propagation delay under 20 ns matched w ithin 1 ns to the other channel ? double current capability by paralleling channels ? standard soic-8 package ? rated from C 40c to +1 25 c ambient ? automotive qualified to aec-q100 (f085 version) applications ? sw itch-mode pow er supplies ? high-efficiency mosfet sw itching ? synchronous rectifier circuits ? dc- to -dc converters ? motor control ? automotive-qualified systems (f085 version) description the fa n3213 and fan3214 dual 4 a gate drivers are designed to drive n-channel enhancement- mode mosfets in low -side sw itching applications by providing high peak current pulses dur ing the short sw itching intervals. they are both available w ith ttl input thresholds. internal circuitry provides an under- voltage lockout function by holding the output low until the supply voltage is w ithin the operating range. in addition, the drivers feature matched internal propagation delays betw een a and b channels for applications requir ing dual gate drives w ith critical timing, such as synchronous rectifiers. this also enables connecting tw o drivers in parallel to effectively double the current capability driving a single mosfet. the fa n3213/14 drivers incorporate miller drive? architecture for the final output stage. this bipolar- mosfet combination provides high current during the miller plateau stage of the mosfet turn-on / turn-off process to minimize sw itching loss, w hile providing rail- to -rail voltage sw ing and reverse current capability. the FAN3213 offers two inverting drivers and the fa n3214 offers tw o non-inverting drivers. both are offered in a standard 8- pi n soic package. FAN3213 fan3214 figure 1. pin configurations 1 nc ina gnd nc vdd inb outa outb 2 3 4 8 6 5 a 7 b 1 nc vdd outa outb 2 3 4 8 6 5 7 a b nc ina gnd inb
www. onsemi.com 2 fan32 13 / fan32 14 dual - 4 a , high - speed , low - side gate drivers ordering information part number logic input threshold package packing method quantity per reel fan3 213t mx dual inverting channels ttl soic - 8 tape & reel 2,500 fan3 214t mx dual non - inverting channels FAN3213tmx _f085 ( 1 ) dual inverting channels fan3214tmx _f085 ( 1 ) dual non - inverting channels note: 1. qualified to aec-q100 package outlines figure 2. soic-8 (top view ) thermal characteristics ( 2 ) package ? jl ( 3 ) ? jt ( 4 ) ? ja ( 5 ) ? jb ( 6 ) ? jt ( 7 ) unit 8 - pin small outline integrated cir cuit (soic) 38 29 87 41 2.3 c/w notes: 2. estimates derived from thermal simulation; actual values depend on the application. 3. theta_jl ( ? jl ): thermal resistance betw een the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a pcb. 4. theta_jt ( ? jt ): thermal resistance betw een the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. 5. theta_ja ( ja ): thermal resistance betw een junction and ambient, dependent on the pcb design, heat sinking, and airflow . the value given is for natural convection w ith no heatsink, using a 2s2p board, as specified in jedec standards jesd51-2, jesd51-5, and jesd51- 7, as appropriate. 6. p si _jb ( ? jb ): thermal characterization parameter providing correlation betw een semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in note 5 . for the soic-8 package, the board reference is defined as the pcb copper adjacent to pin 6. 7. p si _jt ( ? jt ): thermal characterization parameter providing correlation betw een the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in note 5 . 2 3 8 6 1 4 7 5
www. o n semi .com 3 fan32 13 / fan32 14 2 dual - 4 a , high - speed , low - side gate drivers pin configurations FAN3213 fan3214 figure 3. pin configurations (repeated) pin definitions pin n ame pin description 1 nc no connect. this pin can be grounded or left floating. 2 in a input to channel a . 3 gnd ground . c ommon ground referen ce for input and output circuits . 4 in b input to channel b . 5 (FAN3213) gate drive o utput b (inverted from the input): held low unless required input is present and v dd is above uvlo threshold. 5 (fan3214) outb gate drive output b : held low unless required input(s) are present and v dd is above uvlo threshold. 6 vdd supply voltage . provi des pow er to the ic. 7 (FAN3213) gate drive output a (inverted from the input): held low unless required input is present and v dd is above uvlo threshold. 7 (fan3214) outa gate drive output a : held low unless required input(s) are present and v dd is above uvlo threshold. 8 nc no connect. this pin can be grounded or left floating. output logic FAN3213 (x=a or b) fan3214 (x=a or b) inx inx outx 0 1 0 ( 9 ) 0 1 ( 9 ) 0 1 1 note: 9. default input signal if no external connection is made. 1 n c i n a g n d n c v d d i n b o u t a o u t b 2 3 4 8 6 5 a 7 b 1 n c v d d o u t a o u t b 2 3 4 8 6 5 7 a b n c i n a g n d i n b outb outa outx
www. o n semi .com 4 fan32 13 / fan32 14 2 dual - 4 a , high - speed , low - side gate drivers block diagrams figure 4. FAN3213 block diagram figure 5. fan3214 block diagram 6 v d d 7 o u t a v d d _ o k 5 i n a 2 n c 1 g n d 3 u v l o 8 n c i n b 4 o u t b 1 0 0 k : 1 0 0 k : 1 0 0 k : 1 0 0 k : 6 v d d 7 o u t a v d d _ o k 5 i n a 2 n c 1 g n d 3 u v l o 8 n c i n b 4 o u t b 1 0 0 k : 1 0 0 k : 1 0 0 k : 1 0 0 k :
www. o n semi .com 5 fan32 13 / fan32 14 2 dual - 4 a , high - speed , low - side gate drivers absolute maximum ratings stresses exceed ing the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the r ecommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v dd vdd to p gnd - 0.3 20.0 v v in ina and inb to gnd gnd - 0.3 v dd + 0.3 v v out outa and outb to gnd gnd - 0.3 v dd + 0.3 v t l lead soldering temperature (10 s econds) + 260 oc t j junction temperature - 55 + 150 oc t stg storage temperature - 65 + 150 oc recommended operating conditions the recommended operating conditions table defines the conditions for actua l device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet spec ifications. o n semiconductor does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit v dd su pply voltage range 4.5 18.0 v v in input voltage ina and inb 0 v dd v t a operating ambient temperature - 40 + 12 5 oc
www. o n semi .com 6 fan32 13 / fan32 14 2 dual - 4 a , high - speed , low - side gate drivers electrical characteristics unless otherw ise noted, v dd =12 v , t j = - 40c to + 12 5c. currents are defined as positive into the device and ne gative out of the device. symbol parameter conditions min. typ. max. unit s upply fan321xt v dd operating range 4.5 18.0 v i dd supply current, inputs not connected 0.70 0.95 ma v on turn - on voltage ina= v dd , inb = 0 v 3.5 3.9 4.3 v v off turn - off voltag e ina= v dd , inb = 0 v 3.3 3.7 4.1 v fan321xtmx_f085 (automotive - qualified versions) i dd supply current, inputs not connected ( 12 ) 0.70 1.2 0 ma v on turn - on voltage ( 12 ) ina= v dd , inb = 0 v 3. 3 3.9 4. 5 v v off turn - off voltage ( 12 ) ina= v dd , inb = 0 v 3. 1 3.7 4. 3 v inputs v il_t inx logic low threshold 0.8 1.2 v v ih_t inx logic high threshold 1.6 2.0 v fan321xt i in+ non - inverting input in from 0 to v dd - 1.5 175 .0 a i in - inverting input in from 0 to v dd - 17 5 .0 1.5 a v hys_t ttl logic hysteresis voltage 0.2 0.4 0.8 v fan321xtmx_f085 (automotive - qualified versions) i i nx_t non - inverting input current ( 12 ) in = 0 v - 1. 5 1.5 a i i nx_t non - inver ting input current ( 12 ) in = v dd 90 120 175 a i i nx_t inverting input current ( 12 ) in = 0 v - 175 - 120 - 90 a i i nx_t inverting input current ( 12 ) in = v dd - 1. 5 1.5 a v hys_t t tl logic hysteresis voltag e ( 12 ) 0.1 0.4 0.8 v output i sink out current, mid - voltage, sinking ( 10 ) outx at v dd /2, c load =0.22 f, f=1 khz 4.3 a i source out current, mid - voltage, sourcing ( 10 ) outx at v dd /2, c load =0.22 f, f=1 khz - 2.8 a i pk_sink out current, peak, sinking ( 10 ) c load =0.22 f, f=1 khz 5 a i pk_source out current, peak, sourcing ( 10 ) c load = 0.22 f, f=1 khz - 5 a i rvs output reverse current withstand ( 10 ) 500 ma t del.match propagation matching betw een channels ina=inb, outa and outb at 50% point 2 4 ns continued on the following page
www. o n semi .com 7 fan32 13 / fan32 14 2 dual - 4 a , high - speed , low - side gate drivers electrical chara cteristics (continued) unless otherw ise noted, v dd =12 v , t j = - 40c to + 12 5c. currents are defined as positive into the device and negative out of the device. symbol parameter conditions min. typ. max. unit fan321xt t rise output rise time ( 11 ) c load =2200 pf 12 20 ns t fall output fall time ( 11 ) c load =2200 pf 9 17 ns t d1 , t d2 output propagation delay, ttl inputs ( 11 ) 0 - 5 v in , 1 v/ns slew rate 9 17 29 ns fan321xtmx_f085 (automotive - qualified versions) t rise output rise time ( 11 )( 12 ) c load =2200 pf 12 22 ns t fall output fall time ( 11 )( 12 ) c load =2200 pf 9 1 8 ns t d1 , t d2 output propagation delay, ttl inputs ( 11 )( 12 ) 0 5 v in , 1 v/ns slew rate 9 17 32 ns v oh high level output voltage ( 12 ) v oh = v dd C C 9 0 % 1 0 % o u t p u t i n p u t t d 1 t d 2 t r i s e t f a l l v i n l v i n h 9 0 % 1 0 % o u t p u t t d 1 t d 2 t f a l l t r i s e v i n l v i n h i n p u t
www. o n semi .com 8 fan32 13 / fan32 14 2 dual - 4 a , high - speed , low - side gate drivers typical performance characteristics typical characteristics are provided at t a =25c and v dd =12 v unless otherw ise noted. figure 8. i dd (static) vs. supply voltage ( 12 ) figure 9. i dd (static) vs. tem perature ( 12 ) figure 10. i dd (no load) vs. frequency figure 11. i dd (2.2 nf load) vs. frequency figure 12. input thresholds v s. supply voltage figure 13. input thresholds vs. tem perature
www. o n semi .com 9 fan32 13 / fan32 14 2 dual - 4 a , high - speed , low - side gate drivers typical performance characteristics typical characteristics are provided at t a =25c and v dd =12 v unless otherw ise noted. uvlo threshold vs. tem perature figure 14. propagation delay vs. supply voltage figure 15. propagation delay vs. supply voltage figure 16. propagation delays vs. tem perature figure 17. propagation delays vs. tem perature
www. o n semi .com 10 fan32 13 / fan32 14 2 dual - 4 a , high - speed , low - side gate drivers typical performance characteristics typical characteristics are provided at t a =25c and v dd =12 v unless otherw ise noted. figure 18. fall tim e vs. supply voltage figure 19. rise tim e vs. supply voltage figure 20. rise and fall tim e s vs. tem perature figure 21. rise/fall waveform s w ith 2.2 nf load figure 22. rise/fall waveform s w ith 10 nf load
www. o n semi .com 11 fan32 13 / fan32 14 2 dual - 4 a , high - speed , low - side gate drivers typical performance characteristics typical characteristics are provided at t a =25c and v dd =12 v unless otherw ise noted. figure 23. quasi - static source current w ith v dd =12 v ( 13 ) figure 24. quas i - static s ink current w ith v dd =12 v ( 13 ) figure 25. quasi - static source current w ith v dd = 8 v ( 14 ) figure 26. quasi - static s ink current w ith v dd = 8 v ( 14 ) notes: 13. for any inverting inputs pulled low , non - inverting inputs pulled high, or outputs driven high; static idd increases by the current flow ing through the corresponding pull - up/dow n resistor show n in figure 4 and figure 5 . 14. the initial spike in each current w aveform is a measurement artifact caused by the stray inductance of the current - measurement loop. test circuit figure 27. quasi - static i out / v out test circuit 4 7 0 f a l . e l . v d d v o u t 1 f c e r a m i c 4 . 7 f c e r a m i c c l o a d 0 . 2 2 f i o u t i n 1 k h z c u r r e n t p r o b e l e c r o y a p 0 1 5
www. o n semi .com 12 fan32 13 / fan32 14 2 dual - 4 a , high - speed , low - side gate drivers applications i nformation input thresholds the FAN3213 and the fan3214 drivers consist of tw o identical channels that may be used independently at rated current or connected in parallel to double the individual current capacity. the input thresholds meet industry - stand ard ttl - logic thresholds independent of the v dd voltage, and there is a hysteresis voltage of approximately 0.4 v. these levels per mit the inputs to be driven from a range of input logic s ignal levels for w hich a voltage over 2 v is considered logic high. the driving signal for the ttl inputs should have fast rising and falling edges w ith a slew rate of 6 v/s or faster, so a rise time from 0 to 3.3 v should be 550 ns or less. with reduced slew rate, circuit noise could cause the driver input voltage to exc eed the hysteresis voltage and retrigger the dr iver input, causing erratic operation. static supply current in the i dd (static) typical performance characteristics show n in figure 8 and figur e 9 , ea ch curve is produced w ith both inputs floating and both outputs low to indicate the low est static i dd current. for other states, additional current flow s through the 100 k : resistors on the inputs and outputs show n in the block diagram of each part (see figure 4 and figure 5 ) . in these cases, the actual static i dd current is the value obtained from the curves plus this additional current. 0loohu'ulyh?*dwh'ulyh7hfkqrorj\ fa n3213 and fa n3214 gate drivers incorporate the 0loohu 'ulyh? dufklwhfwxuh vkrz q lq figure 28 . for the output stage, a combination of bipolar and mos devices provide large currents over a w ide range of supply voltage and temperature variations. the bipolar devices carry the bulk of the current as out sw ings betw een 1/3 to 2/3 v dd and the mos devices pull the output to the high or low rail. the purp rvh ri wkh 0loohu 'ulyh? dufklwhfwxuh lv wr speed up sw itching by providing high current during the miller plateau region w hen the gate - drain capacitance of the mosfet is being charged or discharged as part of the turn - on / turn - off process. for applicatio ns w ith zero voltage sw itching during the mosfet turn - on or turn - off interval, the driver supplies high peak current for fast sw itching even though the miller plateau is not present. this situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the mosfet is sw itched on. the output pin slew rate is determined by v dd voltage and the load on the output. it is not user adjustable, but a series resistor can be added if a slow er rise or fall time at the mosfet gate is needed. figure 28. 0loohu'ulyh?2xwsxw$ufklwhfwxuh under - voltage lockout the fan321x startup logic is optimized to drive ground - referenced n - channel mosfets w ith an under - voltage lockout ( uvlo) function to ensure that the ic starts up in an orderly fashion. when v dd is rising, yet below the 3.9 v operational level, this circuit holds the output low, regardless of the status of the input pins. after the part is active, the supply voltage must drop 0.2 v before the part shut s dow n. this hysteresis helps prevent chatter w hen low v dd supply voltages have noise from the pow er sw itching. this configuration is not suitable for driving high - side p - channel mosfets because the low output voltage of the driver w ould turn the p - channel mosfet on w ith v dd below 3.9 v. v dd bypass capacitor guidelines to enable this ic to turn a device on quickly, a local high - frequency bypass capacitor, c byp , w ith low esr and esl should be connected betw een the vdd and gnd pins w ith minimal trace length. this capacitor is in addition to bulk electrolytic capacitance of 10 f to 47 f commonly found on driver and controller bias circuits. a typical criterion for choosing the value of c byp is to keep the ripple voltage on the v dd vxsso\wr?7klv lvriwhqdfklhyhgz lwkdydoxh?wlphvwkhhtxlydohqw load capacitance c eqv , defined here as q gate /v dd . ceramic capacitors of 0.1 f to 1 f or larger are common choices, as are dielectrics, such as x5r and x7r, w ith good temperatu re characteristics and high pulse current capability. if circuit noise affects normal operation, the value of c byp may be increased, to 50 - 100 times the c eqv , or c byp may be split into tw o capacitors. one should be a larger value, based on equivalent load capacitance, and the other a s maller value, such as 1 - 10 nf mounted closest to the vdd and gnd pins to carry the higher - frequency components of the current pulses. the bypass capacitor must provide the pulsed current from both of the driver channels and, i f the drivers are sw itching simultaneously, the combined peak current sourced from the c byp w ould be tw ice as large as w hen a single channel is sw itching. i n p u t s t a g e v d d v o u t
www. o n semi .com 13 fan32 13 / fan32 14 2 dual - 4 a , high - speed , low - side gate drivers layout and connection guidelines the fa n3213 and fan3214 gate dr ivers incorporate fast - reacting input circuits, short propagation delays, and pow erful output stages capable of delivering current peaks over 4 a to facilitate voltage transition times from under 10 ns to over 150 ns. the follow ing layout and connection guidelines are strongly recommende d: ? keep high - current output and pow er ground paths separate from logic input signals and signal ground paths. this is especially critical for ttl - level logic thresholds at driver input pins. ? keep the driver as close to the load as possible to minimize the length of high - current traces. this reduces the series inductance to improve high - speed sw itching, w hile reducing the loop area that can radiate emi to the driver inputs and surrounding circuitry. ? if the inputs to a channel are not externally connected, th e internal 100 k : resistors indicated on block diagrams command a low output. in noisy environments, it may be necessary to tie inputs of an unused channel to vdd or gnd using short traces to prevent noise from causing spurious output sw itching. ? many high - speed pow er circuits can be susceptible to noise injected from their ow n output or other external sources, possibly causing output re - triggering. these effects can be obvious if the circuit is tested in breadboard or non - optimal circuit layouts w ith long i nput or output leads. for best results, make connections to all pins as short and direct as possible. ? FAN3213 and fan3214 are pin - compatible w ith many other industry - standard drivers. ? the turn - on and turn - off current paths should be minimized, as discuss ed in the follow ing section. figure 29 show s the pulsed gate drive current path when the gate dr iver is supplying gate charge to turn the mosfet on. the current is supplied from the local bypass capacitor, c byp , and flow s throu gh the driver to the mosfet gate and to ground. to reach the high peak currents possible, the resistance and inductance in the path should be minimized. the localized c byp acts to contain the high peak current pulses w ithin this driver - mosfet circuit, prev enting them from disturbing the sensitive analog circuitry in the pwm controller. figure 29. current path for mosfet turn - on figure 30 show s the current path w hen the gate dr iver turns the mosfet off. ideally, the driver shunts the current directly to the source of the mosfet in a s mall circuit loop. for fast turn - off times, the resistance and inductance in this path should be minimized. figure 30. current path for mosfet turn - off p w m v d s v d d c b y p f a n 3 2 1 x p w m v d s v d d c b y p f a n 3 2 1 x
www. o n semi .com 14 fan32 13 / fan32 14 2 dual - 4 a , high - speed , low - side gate drivers operatio nal waveforms at pow er - up, the driver output remains low until the v dd voltage reaches the turn - on threshold. the magnitude of the out pulses rises w ith v dd until steady - state v dd is reached. the non - inverting operation illustrated in figure 31 shows that the output remains low until the uvlo threshold is reached, then the output is in - phase w ith the input. figure 31. non - inverting startup waveform s the inverting configuration of startup w aveforms are show n i n figure 32 . with in+ tied to v dd and the input signal applied to in , the out pulses are inverted w ith respect to the input. at pow er - up, the inverted output remains low until the v dd voltage reaches the turn - on threshold, the n it follow s the input w ith inverted phase. figure 32. inverting startup waveform s v d d i n + i n - o u t t u r n - o n t h r e s h o l d v d d i n + ( v d d ) i n - o u t t u r n - o n t h r e s h o l d
www. o n semi .com 15 fan32 13 / fan32 14 2 dual - 4 a , high - speed , low - side gate drivers thermal guidelines gate dr ivers used to sw itch mosfets and igbts at high frequencies can dissipate s ignificant amounts of pow er. it is important to de ter mine the driver pow er dissipation and the resulting junction temperature in the application to ensure that the part is operating w ithin acceptable temperature limits. the total pow er dissipation in a gate dr iver is the sum of tw o components, p gate and p dynamic : p total = p gate + p dynamic ( 1 ) p gate ( gate driving loss ) : the most significant pow er loss results from supplying gate current (charge per unit time) to sw itch the load mosfet on and off at the sw itching frequ ency. the pow er dissipation that results from dr iving a mosfet at a specified gate - source voltage, v gs , w ith gate charge, q g , at sw itching frequency, f sw , is determined by: p gate = q g ?9 gs ? f sw ?q ( 2 ) w here n is th e number of driver channels in use ( 1 or 2). p dynamic ( dynamic pre - drive / shoot - through current ) : a pow er loss resulting from internal current consumption under dynamic operating conditions, including pin pull - up / pull - dow n resistors . the internal curre nt consumption ( i dynamic ) can be estimated using the graphs in figure 10 of the typical perfor mance characteristics to deter mine the current i dynamic draw n from v dd under actual operating conditions: p dynamic = i dynamic ?9 dd ? n ( 3 ) where n is the number of driver ics in use . note that n is usually be one ic even if the ic has tw o channels , unless two or more . driver ics are in parallel to drive a large load. once the pow er dissipated in t he driver is deter mined, the driver junction rise w ith respect to circuit board can be evaluated using the follow ing ther mal equation, assuming \ j b w as determined for a similar ther mal design (heat sinking and air flow ) : t j = p total ? \ j b + t b ( 4 ) w here: t j = driver junction temperature; \ j b = (psi) thermal characterization parameter relating temperature rise to total pow er dissipation ; and t b = board temperature in location as defined in the thermal characteristics ta ble. to give a numerical example, assume for a 12 v v dd (vibas) system, the synchronous rectifier sw itches of figure 33 have a total gate charge of 60 nc at v gs = 7 v. therefore, tw o devices in parallel w ould have 120 nc gate charge. at a sw itching frequency of 300 khz, the total pow er dissipation is: p gate = 120 q&? 9? n+] ? 04 w ( 5 ) p dynamic = 3 . 0 p$? 12 9? 1 = 0.0 36 w ( 6 ) p total = 0. 540 w ( 7 ) the soic - 8 has a junction - to - board ther mal characterization parameter of \ j b = 42c/w. in a system application, the localized temperature around the device is a function of the layout and construction of the pcb along w ith airflow across the surfaces. to ensure reliable operation, the maximum junction temperature of the device must be prevented from exceeding the maximum rating of 150c; w ith 80% derating, t j w ould be limited to 120c. rearranging equation 4 deter mines the board temperature required to maintain the junction temperature below 120c: t b,max = t j - p total ? \ j b ( 8 ) t b,max = 120c 0.5 4 :??&: 7 c ( 9 )
www. o n semi .com 16 fan32 13 / fan32 14 2 dual - 4 a , high - speed , low - side gate drivers ty pical application diagrams figure 33. high - current forw ard converter w ith synchronous rectification figure 34. center - tapped bridge output w ith synchronous rectifiers figure 35. secondary controlle d full bridge w ith current doubler output, synchronous rectifiers (sim plified) v i n p w m 1 2 3 6 7 8 4 5 t i m i n g / i s o l a t i o n v o u t f a n 3 2 1 4 v b i a s f a n 3 2 1 4 1 2 3 6 7 8 4 5 v d d g n d b a p w m - a p w m - b p w m - c p w m - d s e c o n d a r y p h a s e s h i f t c o n t r o l l e r v i n q a q b q c q d s r - 2 s r - 1 f a n 3 2 1 4 f a n 3 2 2 5 c f a n 3 2 2 5 c
www. o n semi .com 17 fan32 13 / fan32 14 2 dual - 4 a , high - speed , low - side gate drivers table 1. related products type part num ber gate drive ( 15 ) (sink/src) input threshold logic package single 1 a fan3111c +1.1 a / - 0.9 a cmos single channel of dual - input/single - output sot23 - 5, mlp6 single 1 a fan3111e +1.1 a / - 0.9 a external ( 16 ) single non - inverting channel with external reference sot23 - 5, mlp6 single 2 a fan3100c +2.5 a / - 1.8 a cmos single channel of two - input/one - output sot23 - 5, mlp6 single 2 a fan3100t +2.5 a / - 1.8 a ttl single channel of two - input/one - output sot23 - 5, mlp6 single 2 a fan3180 +2.4 a / - 1.6 a ttl single non - inverting channel + 3.3 v ldo sot23 - 5 dual 2 a fan3216t +2.5 a / - 1.8 a ttl dual inverting channels soic8 dual 2 a fan3217t +2.5 a / - 1.8 a ttl dual non - inverting channels soic8 dual 2 a fan3226c +2.4 a / - 1.6 a cmos dual inverting channels + dual enable soic8, mlp8 dual 2 a fan3226t +2.4 a / - 1. 6 a ttl dual inverting channels + dual enable soic8, mlp8 dual 2 a fan3227c +2.4 a / - 1.6 a cmos dual non - inverting channels + dual enable soic8, mlp8 dual 2 a fan3227t +2.4 a / - 1.6 a ttl dual non - inverting channels + dual enable soic8, mlp8 dual 2 a f an3228c +2.4 a / - 1.6 a cmos dual channels of two - input/one - output, pin config.1 soic8, mlp8 dual 2 a fan3228t +2.4 a / - 1.6 a ttl dual channels of two - input/one - output, pin config.1 soic8, mlp8 dual 2 a fan3229c +2.4 a / - 1.6 a cmos dual channels of two - input/one - output, pin config.2 soic8, mlp8 dual 2 a fan3229t +2.4 a / - 1.6 a ttl dual channels of two - input/one - output, pin config.2 soic8, mlp8 dual 2 a fan3268t +2.4 a / - 1.6 a ttl 20 v non - inverting channel (nmos) and inverting channel (pmos) + dual enables soic8 dual 2 a fan3278t +2.4 a / - 1.6 a ttl 30 v non - inverting channel (nmos) and inverting channel (pmos) + dual enables soic8 dual 4 a FAN3213t +2.5 a / - 1.8 a ttl dual inverting channels soic8 dual 4 a fan3214t +2.5 a / - 1.8 a ttl dual non - inverting channels soic8 dual 4 a fan3223c +4.3 a / - 2.8 a cmos dual inverting channels + dual enable soic8, mlp8 dual 4 a fan3223t +4.3 a / - 2.8 a ttl dual inverting channels + dual enable soic8, mlp8 dual 4 a fan3224c +4.3 a / - 2.8 a cmos dual non - inv erting channels + dual enable soic8, mlp8 dual 4 a fan3224t +4.3 a / - 2.8 a ttl dual non - inverting channels + dual enable soic8, mlp8 dual 4 a fan3225c +4.3 a / - 2.8 a cmos dual channels of two - input/one - output soic8, mlp8 dual 4 a fan3225t +4.3 a / - 2. 8 a ttl dual channels of two - input/one - output soic8, mlp8 single 9 a fan3121c +9.7 a / - 7.1 a cmos single inverting channel + enable soic8, mlp8 single 9 a fan3121t +9.7 a / - 7.1 a ttl single inverting channel + enable soic8, mlp8 single 9 a fan3122 c +9 .7 a / - 7.1 a cmos single non - inverting channel + enable soic8, mlp8 single 9 a fan3122 t +9.7 a / - 7.1 a ttl single non - inverting channel + enable soic8, mlp8 dual 12 a fan3240 +12.0 a ttl dual - coil relay driver, timing config. 0 soic8 dual 12 a fan3241 +12.0 a ttl dual - coil relay driver, timing config. 1 soic8 notes: 15. typical currents w ith outx at 6 v and v dd =12 v. 16. thresholds proportional to an externally supplied reference voltage.
www. o n semi .com 18 fan32 13 / fan32 14 2 dual - 4 a , high - speed , low - side gate drivers physical dimensions figure 36. 8 - lead sm all outline integrated circuit ( soic ) 8 0 see detail a notes: a) this package conforms to jedec ms-012, variation aa. b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m e) drawing filename: m08arev16 land pattern recommendation seating plane c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 b 5 a 5.60 0.65 1.75 1.27 6.000.20 3.900.10 4.900.10 1.27 0.420.09 0.1750.075 1.75 max 0.36 (0.86) r0.10 r0.10 0.650.25 (1.04) option a - bevel edge option b - no bevel edge 0.25 c b a 0.10 0.220.03 (0.635)
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